About Perry

I’m a Junior at the Milwaukee School of Engineering pursuing a bachelor’s in computer engineering. With over 10 years of hobbyist experience with RTL and hardware development - my passion for computers and hardware started early at just 10 years old. I’ve developed custom software/hardware solutions that have been deployed across the country through previous internship experience and I’m eager to continue applying my passion, skill, knowledge and love for the field of computer engineering to create more innovative and elegant solutions.

Skills

  • Python (Tkinter, PyQt, matplotlib, tensorflow, pytorch, transformers, pandas, pyserial, Qiskit, Flask)
  • VHDL
  • Verilog/SystemVerilog
  • C
  • C++
  • Java
  • Kotlin
  • JavaScript
  • HTML/CSS
  • Bash
  • TCL (Tcl/Tk)
  • Perl
  • Git
  • Jenkins
  • AXI4, AXI4-Lite
  • Quartus, Modelsim, Vivado, Vitis HLS
  • RISC-V, ARM, Microblaze
  • UVM, CocoTB, PyUVM
  • MATLAB, Simulink, Speedgoat HIL
  • I2C, SPI, Serial, MII
  • Logic Analyzers, JTAG, PLL, DLL
  • NI Multisim
  • Digital Signal Processing
  • Superscalar and Parallel Architectures
  • PCB Design (EasyEDA, JLCPCB)
  • Jupyter Notebook
  • MS Office, Excel

Websites

Certifications

Projects

  • CSMA/CD Networking Protocol Implemented and Pipelined on Artix 7 FPGA | 2025

    Technologies Used: VHDL, QuestaSim, TCL, Vivado, Manchester Encoding, EasyEDA, JLCPCB

    • Project Objective: Implement MSOE networking protocol in pure hardware - Deep pipelines.
    • Implementation tested up to 2mbps with >98% accuracy.
    • Implementation recognizes collisions mid transmission and knows to retransmit packets to directed device when network returns idle, successfully interacting over RJ45 switch.
    • Features: CRC8, packet construction around message, 255 unique addresses, broadcasting address, and two UART communication ports for sending and reading network messages.
    • The two UART boards that talk to the FPGA feature a CP2102 and use a USB type C connector; these were developed in EasyEDA and printed through JLCPCB.
    • Developed TCL/Tk scripts for building project and running testbenches on new git clone.
    • Eight-stage calibration pipeline on the Manchester decoder to handle 25% tolerance.
    • Result: Successfully achieved interoperability with another implementation through switch.
  • Broadcast UDP Packets with Artix 7 FPGA through Homelab Network Switch | 2025

    Technologies Used: VHDL, Vivado, MII, UDP

    • Project Objective: Broadcast hardcoded UDP packets to contain message payloads.
    • Designed and implemented a pure hardware solution for the Artix 7 FPGA that can transmit UDP packets over ethernet through the PHY via MII interface connected to the PL.
    • UDP packets contain custom payloads any device in my home lab network can receive.
    • Result: Completed – College Junior Year, plans to expand functionality further.
  • Inference of Quantized Neural Networks with Ultrascale+ FPGAs | 2024–2025

    Technologies Used: Python, Vivado, Vitis (HLS), GitLab, Pytorch, Tensorflow

    • Project Objective: Run quantized neural networks in parallel >150MHz on Ultrascale+.
    • Designed and developed Pytorch & Tensorflow python programs to train sequential neural networks with ReLU activation to predict patterns for people with diabetes, sensor failure, and nonlinear abnormal trigonometry functions.
    • Developed python scripts to extract weights and biases from trained networks.
    • Developed python scripts to quantize exported weights and biases in 16/8/4bit, and ternary.
    • Developed python scripts to write and save new VHDL hardware entities and packages for synthesizing hardware capable of inference – deep pipelining was utilized for timing.
    • Result: <1Watt for inference of 1000neurons – Expanding functionality.
  • Create my own Chatbot Server Stack | 2024–2025

    Technologies Used: Wireguard, Python (llama_cpp, HTTPServer, Flask), HTML, CSS, JS

    • Project Objective: Local hosted LLM accessible through webserver on VPN subnet.
    • Local inference of a quantized 8billion parameter LLM using llama_cpp.
    • I developed and deployed a frontend webpage hosted on my desktop that would send and receive responses generated by the LLM to the site.
    • HTTP server on 10.0.0.2:5000 listens for incoming payload, processes JSON payload, responds with JSON message.
    • Custom commands on frontend user input for clearing screen and providing help messages.
    • Enter questions are sent to the Flask server on 10.0.0.2:5001, this is forwarded to the LLM.
    • Result: From anywhere in the world, I can access my VPN server which gives me access to my locally hosted alliterated LLM.
  • FPGA Based Arbitrary Waveform Generator with Custom PCBs | 2023–2024

    Technologies Used: VHDL, Vivado, C, CubeIDE, SPI

    • Project Objective: FPGA – Parallel DAC Waveform generator.
    • Designed and printed PCBs each with one parallel DAC and ADC with two SMA connectors.
    • Parallel DACs connected to an Artix 7 FPGA development board, user toggles switches on the FPGA board to change the frequency of the output wave and the type.
    • Waves implemented (square, sine, triangle, and sawtooth).
    • Waveform fed into onboard ADC of an STM32F411 microcontroller, driven by interrupts.
    • STM32 drives a LED dot matrix display to showcase the varying voltage levels of waveform.
    • Result: Generated various waveforms through my custom PCBs, demo on perrynewlin.com.
  • Develop Website for Phasor Calculation & Testbenches Generation | 2023–2025

    Technologies Used: HTML, CSS, JS (chart.js, three.js)

    • Project Objective: Create a website for calculating phasors.
    • Designed and created easytrig.com – a website that makes math operations pertaining to circuit analysis far easier to perform on mobile devices.
    • Render outputs from OpenAI’s ChatGPT in markdown and convert to PDF.
    • Add, subtract, multiply, and divide phasors with steps rendered in real-time.
    • Render phasors as sinusoids with zooming and autozoom features.
    • Plot imaginary numbers as vectors and have length calculated in real-time.
    • Added tool to generate VHDL testbench boilerplate code based on entity ports.
    • Result: Easytrig gets 1000+ monthly visits, bringing free and powerful tools to the masses.
  • Develop, Synthesize, and Implement soft ARMv4 Processor in VHDL | 2022

    Technologies Used: VHDL, Quartus, ModelSim

    • Project Objective: ARM processor on Intel DE10 FPGA development board.
    • In Digital Logic II I implemented the ARMv4 ISA as a soft processor in VHDL on the DE10.
    • Implemented w/ VHDL: instruction fetch, decode, execute, memory, and register writeback.
    • Verified program execution, and writeback functionality with comprehensive testbenches.
    • IROM compatible with the following assembly: MOV, LDR, STR, ADD, SUB, CMP, BEQ.
    • Result: Executed a program to light up LEDs that utilized branches, arithmetic, and load/store.
  • Custom Handheld Microcontroller Game Console | 2020–2021

    Technologies Used: C, Arduino, I2C, UI design, FRAM, JTAG (AVR Programmer), PCB Design

    • Project Objective: Portable handheld game console using custom PCBs.
    • Designed custom board using 32u4 microcontroller.
    • Designed and programmed custom games rendered on a 128x32 I2C screen.
    • Games which include object avoidance with built in difficulty increase as score increments.
    • Designed custom FRAM logic to store user scores after console shutdown.
    • Result: Could play custom made two-color games in a case < 1” wide at more than 40 frames.
  • Accessibility OLED Watch to Display my Class Schedule | 2018

    Technologies Used: C, Arduino, I2C, UI design

    • Project Objective: Create a watch using a low powered MCU that displays my class schedule.
    • Designed wristwatch with 16u4 development board, LiPo battery, & I2C OLED display.
    • Designed U.I to display class schedule for which day of week it was.
    • Displayed schedule could be cycled using a single push button input, debounced.
    • Result: No longer had to remember a long schedule, just look at my custom watch!
  • Simple as Possible 1 Single Cycle Computer | 2015–2016

    Technologies Used: 74LS series ICs, EEPROMs, Oscilloscope, Function Generator

    • Project Objective: Build 8-bit SAP-1 Computer From Scratch.
    • Used 74LS series logic chips and other DIP based chips to build an 8bit computer entirely on breadboards.
    • After 7 months it was completed and was able to run the JMP command.
    • After 8 months it could play the Fibonacci sequence all on its own.
    • Features: 8-Bit instruction register, 4-bit program counter, 8-Bit accumulator and B-register.
    • Inspired by Ben Eater.
    • Result: Can perform a jump instruction and run a loaded program in the EEPROM.

Relevant Coursework

  • Superscalar, Multicore, and Multiprocessor Architecture
    Course Code: CPE 4510 — Milwaukee School of Engineering
  • Advanced Embedded Systems
    Course Code: CPE 3600 — Milwaukee School of Engineering
  • Computer Architecture
    Course Code: CE 1921 — Milwaukee School of Engineering
  • Differential Equations
    Course Code: MTH 2130 — Milwaukee School of Engineering
  • Digital Logic I
    Course Code: CE 1901 — Milwaukee School of Engineering
  • Digital Logic II
    Course Code: CE 1911 — Milwaukee School of Engineering
  • Discrete Mathematics
    Course Code: MTH 2310 — Milwaukee School of Engineering
  • Embedded Systems
    Course Code: CPE 2610 — Milwaukee School of Engineering
  • Ethics for Managers & Engineers
    Course Code: PHL 3101 — Milwaukee School of Engineering
  • Physics II — Electromagnetism
    Course Code: PH 2021 — Milwaukee School of Engineering
  • Probability and Statistics
    Course Code: MTH 2480 — Milwaukee School of Engineering
  • Systems Programming
    Course Code: CPE 2600 — Milwaukee School of Engineering
  • Waves, Relativity, Thermodynamics
    Course Code: PH 1980T — Milwaukee School of Engineering

Gallery

Interesting pictures I take during the creative process.

To prevent un-authorized use, a vast majority of the gallery is hidden (>500Pictures/Videos). Thank you for understanding.

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FPGA DAC Driver & STM32 Oscilloscope
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Custom RM69330 Driver Board (1.8V PSU, UART, Level Shifter)
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Mutator Setup UVC Lighting & Actuators
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Mutator Soft X-Rays
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Early RM69330 PCB Level Shifter Attempt